With the advent of the technology of wafer level packaging (WLP), wafer level test (WLT) and wafer level burn-in (WLBI), it has become necessary to equip semiconductor substrates or semiconductor chips with electrically connecting elements which have a built-in compliance (flexibility) in the direction of the X, Y and Z axes.
A further requirement is that it is necessary to provide a stable electrical connection from the semiconductor chip to the printed circuit board. In the case of a copper interconnect, the metal must be protected against oxidation and corrosion. This is usually realized by encapsulating the copper with another, more resistant metal such as e.g. gold.
A disadvantage of such protection is that an additional photolithographic stage has hitherto been required in fabrication. This makes the process more costly and more complex.
FIG. 6 shows the cross section of a semiconductor substrate 1 provided with an interconnect according to a customary method. A layer 2 made of a titanium compound, which serves as a diffusion barrier for all subsequent coating steps, is applied to the substrate 1 by the sputtering method. Above it, it is adjoined by a copper carrier layer 3, which is applied by the sputtering method and is required in order, as short-circuit layer, to enable a subsequent electrophoretic coating with a copper interconnect 4, and as diffusion barrier. A photolithographically patterned mask 7 made of photoresist that can be electrodeposited determines the width of the interconnect 4. A nickel layer 5 is applied above the copper interconnect 4. Above the nickel layer, the latter is adjoined by a gold layer 6, which is required for wetting with solder since adequate wetting of the surface with solder does not take place on nickel. The nickel layer 5 serves as a diffusion barrier between the copper layer 4 and the gold layer 6, since the gold would otherwise diffuse completely into the copper.
FIG. 7 shows the arrangement after the removal of the mask 7 made of the photoresist that can be electrodeposited. The sidewalls 8 of the copper interconnect 4 are uncovered and thus exposed to corrosion.
FIG. 8 shows the arrangement after the structure etching of the copper carrier layer 3 and the layer 2 made of the titanium compound. The sidewalls 8 of the copper interconnect 4 and of the copper carrier layer 3 are uncovered and can corrode. An undercut 11 can impair the adhesion of this interconnect arrangement on the substrate 1.
In the case of the non-compliant (-flexible) wafer level packages (WLP) (e.g. flip-chip), a corrosion protection for the copper constituents of this interconnect arrangement can be applied by reliquefying solder which is applied to the metal interconnect arrangement from above (underbump metallurgy UBM). This reliquefaction allows the solder (SnPb) to flow over the edges of the copper and to encapsulate the copper in the process. Other methods utilize a further photolithographic step and encapsulate the metal either with a dielectric, such as e.g. benzocyclobutene (BCB), or other corrosion-resistant materials.
In the case of the compliant (flexible) wafer level packages (WLP), no encapsulation method has been disclosed heretofore.
Reliquefying the solder in order thereby to encapsulate the copper requires a high outlay and is very cost-intensive. This is also technically infeasible in the case of compliant electrical connecting elements because the entire interconnect would have to be covered with solder in this case. The use of an additional photolithographic step in order to ensure encapsulation of the metal is likewise associated with a high outlay and high costs.